High-speed circuits are increasingly demanding that clock distributions have low skew. Various design techniques may be utilized to help achieve a desired clock skew for a given design. One such technique is through the use of delay lock loops.
Delay lock loops delay the outgoing clock signals that are generated from one or more input signals. That is, delay lock loops insert delays between an input clock and output clock to control the time that a clock is to be asserted. These delays can be utilized to maintain clock outputs at precise times taking into account process and temperature variations. In various implementations of a delay lock loop, the value of the delay may be controlled by a phase detector that compares a reference clock to the output clock. As necessary to maintain a desired output clock, the phase detector adjusts the delay driving the output clock.